org 0x0

start:
    ;clr a; cpl a
	clr a
	mov r0,a
	cpl a
	mov r1,a
	
	;rl a,rlc a
	mov a,#0x73
	rl a
	mov r2,a
	
	mov psw,#0x80
	rlc a
	mov r3,a
	
	mov psw,#0x00
	rlc a
	mov r4,a
	
	mov a,#0x73
	rr a
	mov r5,a
	
	mov psw,#0x80
	rrc a
	mov r6,a
	
	mov psw,#0x00
	rrc a
	mov r7,a
	
	sjmp $
;for test
REG_SP     EQU 0x1000
REG_A      EQU 0x1001
REG_B      EQU 0x1002
REG_PSW    EQU 0x1003
REG_PC     EQU 0x1004
REG_DPTR   EQU 0x1005
CYCLE      EQU 0x1006
REG_R0     EQU 0x2000
REG_R1     EQU 0x2001
REG_R2     EQU 0x2002
REG_R3     EQU 0x2003
REG_R4     EQU 0x2004
REG_R5     EQU 0x2005
REG_R6     EQU 0x2006
REG_R7     EQU 0x2007
REG_END    EQU 0x2FFF
	org 0x600
	dw REG_SP,    0x7
	dw REG_A,     0x6e
	dw REG_B,     0x0
	dw REG_PC,    0x20
	dw REG_DPTR,  0x0
	dw CYCLE,     28
	dw REG_R0,    0x0
	dw REG_R1,    0xff
	dw REG_R2,    0xe6
	dw REG_R3,    0xcd
	dw REG_R4,    0x9a
	dw REG_R5,    0xb9
	dw REG_R6,    0xdc
	dw REG_R7,    0x6e
	dw REG_END
end
	